`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:48:56 03/31/2014 
// Design Name: 
// Module Name:    vga_display 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module vga_display(clk, rst, data_in, HS, VS, red, green, blue);
	 input clk, rst;
	 input [2:0] data_in;
	 output HS, VS;
	 output [2:0] red, green;
	 output [1:0] blue;
	 
	 //reg HS, VS;
	 reg [2:0] red, green;
	 reg [1:0] blue;
	 reg [7:0] data;//store data read from bcd
	 
	 wire blank;
	 wire [10:0] hcounter, vcounter;
	 wire pix_clk, refresh_clk, effective;
	 
	 wire [7:0] data_out;
	 
	 clock_div divider(
	 .clk(clk), 
	 .vga_clk(pix_clk),
	 .refresh_clk(refresh_clk)
    );
	 
	 
   vga_controller controller(
	.pixel_clk(pix_clk),
	.HS(HS),
	.VS(VS),
	.hcounter(hcounter),
	.vcounter(vcounter),
	.blank(blank));

	
	display_area(
	.clk(refresh_clk), 
	.status(data_in), 
	.hcounter(hcounter), 
	.vcounter(vcounter), 
	.effective(effective)
    );
	
	

	 always@(posedge clk)
	 if(!blank && effective) {red,green,blue} = 8'hff;
		
	 else {red,green,blue} = 8'b00000000;

		
	 

endmodule



